View 844008AKI-46LF_8967874.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

femtoclock ? crystal-to-lvds clock generator 844008i-46 da ta sheet 844008i-46 revision a 11/6/15 1 ?2015 integrated device technology, inc. g eneral d escription the 844008i-46 is a 10gb ethernet clock generator and a member of the hiperclocks? family of high performance devices from idt. the 844008i-46 can synthesize 156.25mhz or 100mhz with a 25mhz crystal. it has a total of 8 lvds outputs. the 844008i-46 has excellent phase jitter performance and is packaged in a 32 lead vfqfn package , making it ideal for use in systems with limited board space. f eatures ? eight differential lvds outputs ? crystal oscillator interface designed for 18pf parallel resonant crystals ? supports the following output frequencies: 156.25mhz or 100mhz ? vco frequency: 625mhz or 600mhz ? rms phase jitter @ 156.25mhz, using a 25mhz crystal (1.875mhz - 20mhz): 0.45ps (typical) ? full 2.5v supply mode ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) packages ? for functional replacement part use 8t49n285 p in a ssignment phase detector vco 625mhz or 600mhz fb = 25 or 24 osc q0:q7 nq0:nq7 xtal_in xtal_out freq_sel oe pulldown pullup 25mhz 4 or 6 8 8 b lock d iagram 24 23 22 21 20 19 18 17 nc oe gnd nq7 q7 v ddo nq6 q6 q0 nq0 gnd q1 nq1 v ddo q2 nq2 q3 nq3 gnd q4 nq4 v ddo q5 nq5 v dda freq_sel v dd nc nc xtal_in xtal_out gnd ics844008i-46 32-lead vfqfn 5mm x 5mm x 0.925mm pack- age body k package top view 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 f requency s elect f unction t able input fb divider output divider vco (mhz) output frequency (mhz) xtal frequency (mhz) freq_sel 25 0 25 4 625 156.25 (default) 25 1 24 6 600 100
femtoclock? crystal-to-lvds clock generator 844008i-46 data sheet 2 revision a 11/6/15 t able 1. p in d escriptions t able 2. p in c haracteristics symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf r pulldown input pulldown resistor 51 k pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values.
revision a 11/6/15 844008i-46 d ata sheet 3 femtoclocks? crystal-to-lvds clock generator t able 4a. p ower s upply dc c haracteristics , v dd = v ddo = 2.5v5%, t a = -40c to 85c t able 4b. lvcmos / lvttl dc c haracteristics , v dd = v ddo = 2.5v5%, t a = -40c to 85c a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o (lvds) continuous current 10ma surge current 15ma package thermal impedance, ja 37c/w (0 mps) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress speci? cations only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. symbol parameter test conditions minimum typical maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current oe v dd = v in = 2.625 5 a freq_sel v dd = v in = 2.625 150 a i il input low current oe v dd = 2.625v, v in = 0v -150 a freq_sel v dd = 2.625v, v in = 0v -5 a symbol parameter test conditions minimum typical maximum units v dd core supply voltage 2.375 2.5 2.625 v v dda analog supply voltage v dd ? 0.25 2.5 v dd v v ddo output supply voltage 2.375 2.5 2.625 v i dd power supply current 60 ma i dda analog supply current 25 ma i ddo output supply current 140 ma symbol parameter test conditions minimum typical maximum units v od differential output voltage 247 340 454 mv v od v od magnitude change 50 mv v os offset voltage 1.10 1.25 1.375 v v os v os magnitude change 50 mv t able 4c. lvds dc c haracteristics , v dd = v ddo = 2.5v5%, t a = -40c to 85c
femtoclock? crystal-to-lvds clock generator 844008i-46 data sheet 4 revision a 11/6/15 t able 5. c rystal c haracteristics parameter test conditions minimum typical maximum units mode of oscillation fundamental frequency 25 mhz equivalent series resistance (esr) 50
revision a 11/6/15 844008i-46 data sheet 5 femtoclocks? crystal-to-lvds clock generator t ypical p hase n oise at 156.25mh z 156.25mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.45ps (typical) o ffset f requency (h z ) dbc hz n oise p ower ? ? ? ? ? ?
femtoclock? crystal-to-lvds clock generator 844008i-46 data sheet 6 revision a 11/6/15 p arameter m easurement i nformation rms p hase j itter 2.5v lvds o utput l oad ac t est c ircuit o utput s kew c ycle - to -c ycle j itter o utput r ise /f all t ime o utput d uty c ycle /p ulse w idth /p eriod
revision a 11/6/15 844008i-46 data sheet 7 femtoclocks? crystal-to-lvds clock generator d ifferential o utput v oltage s etup o ffset v oltage s etup p arameter m easurement i nformation , continued a pplication i nformation as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter per- formance, power supply isolation is required. the 844008i-46 provides separate power supplies to isolate any high switch- ing noise from the outputs to the internal pll. v dd , v dda , and v ddo should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v cc pin and also shows that v dda requires that an additional 10
femtoclock? crystal-to-lvds clock generator 844008i-46 data sheet 8 revision a 11/6/15 c rystal i nput i nterface the 844008i-46 has been characterized with an 18pf parallel resonant crystals. the capacitor values shown in f igure 2. c rystal i npu t i nterface figure 2 below were determined using a 25mhz parallel resonant crystal and were chosen to minimize the ppm error. f igure 3. g eneral d iagram for lvcmos d river to xtal i nput i nterface lvcmos to xtal i nterface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 3. the xtal_out pin can be left oating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this con guration requires that the output impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 r2 zo = 50 vdd ro zo = ro + rs r1 vdd xtal_in xtal_out .1uf rs xtal_in xtal_out x1 18pf parallel crystal c1 27pf c2 27pf i nputs : lvcmos c ontrol p ins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k
revision a 11/6/15 844008i-46 data sheet 9 femtoclocks? crystal-to-lvds clock generator 2.5v lvds d river t ermination figure 5 shows a typical termination for lvds driver in characteristic impedance of 100 2.5v 100 ohm differential transmission line 2.5v lvds_driv er r1 100 + - 100 figure 4. the solderable area on the pcb, as de ned by the solder mask, should be at least the same size/ shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. suf cient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application speci c and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, refer to the application note on the surface mount assembly of amkor?s thermally/electrically enhance leadfame base package, amkor technology.
femtoclock? crystal-to-lvds clock generator 844008i-46 data sheet 10 revision a 11/6/15 s chematic l ayout figure 6 shows an example of 844008i-46 application schematic. in this example, the device is operated at v dd = v ddo = 3.3v. the 18pf parallel resonant 25mhz crystal is used. the c1 = 27pf and c2 = 27pf are recommended to logic input pins c4 10uf nq2 oe r1 10 nq4 vddo set logic input to '0' to logic input pins freq_sel zo = 50 ohm zo = 50 ohm r4 50 nq7 q7 q6 nq0 c1 27pf rd2 1k nq6 v dd= v ddo=3.3v vdd q7 nq1 q3 r2 100 x1 25mhz vdd vddo gnd nq3 q4 ru2 not install + - vddo c2 27pf c9 0.1uf set logic input to '1' zo = 50 ohm logic control input examples r3 50 c3 0.01u q5 vdda nq5 nq6 q1 c7 0.1uf rd1 not install q2 ru1 1k c5 0.1uf zo = 50 ohm q6 c8 0.1uf vdd nq7 18pf q0 vdd + - u1 ics844008i-46 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 q0 nq0 gnd q1 nq1 vddo q2 nq2 q3 nq3 gnd q4 nq4 vddo q5 nq5 q6 nq6 vddo q7 nq7 gnd oe nc gnd xtal_out xtal_in nc nc vdd freq_sel vdda c6 0.1uf alternate lvds termination for frequency accuracy. for different board layout, the c1 and c2 may be slightly adjusted for optimizing frequency accuracy. two examples of lvds for receiver without built-in termination are shown in this schematic. f igure 6. 844008i-46 s chematic l ayout
revision a 11/6/15 844008i-46 d ata sheet 11 femtoclocks? crystal-to-lvds clock generator p ower c onsiderations this section provides information on power dissipation and junction temperature for the 844008i-46. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 844008i-46 is the sum of the core power plus the analog power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 2.5v + 5% = 2.625v, which gives worst case results. ? power (core) max = v dd_max * (i dd_max + i dda_max + i ddo_max ) = 2.625v * (60ma + 25ma + 140ma) = 590.625mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air ? ow and a multi-layer board, the appropriate value is 37c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.591w * 37c/w = 106.8c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air ? ow, and the type of board (single layer or multi-layer). t able 7. t hermal r esistance ja for 32-l ead vfqfn, f orced c onvection ja vs. air flow (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 37.0c/w 32.4c/w 29.0c/w
femtoclock? crystal-to-lvds clock generator 844008i-46 data sheet 12 revision a 11/6/15 r eliability i nformation t ransistor c ount the transistor count for 844008i-46 is: 2993 t able 8. ja vs . a ir f low t able for 32 l ead vfqfn ja vs. air flow (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 37.0c/w 32.4c/w 29.0c/w
revision a 11/6/15 844008i-46 d ata sheet 13 femtoclocks? crystal-to-lvds clock generator p ackage o utline - k s uffix for 32 l ead vfqfn t able 9. p ackage d imensions reference document: jedec publication 95, mo-220 note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this drawing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 9 below. jedec variation all dimensions in millimeters (vhhd -2/ -4) symbol minimum maximum n 32 a 0.80 1.0 a1 0 0.05 a3 0.25 reference b 0.18 0.30 e 0.50 basic n d 8 n e 8 d, e 5.0 basic d2, e2 3.0 3.3 l 0.30 0.50
femtoclock? crystal-to-lvds clock generator 844008i-46 data sheet 14 revision a 11/6/15 t able 10. o rdering i nformation part/order number marking package shipping packaging temperature 844008AKI-46LF ics008ai46l 32 lead ?lead-free? vfqfn tray -40c to 85c 844008AKI-46LFt ics008ai46l 32 lead ?lead-free? vfqfn 1000 tape & reel -40c to 85c note: parts that are ordered with an ?lf? suf x to the part number are the pb-free con guration and are rohs compliant.
revision a 11/6/15 844008i-46 d ata sheet 15 femtoclocks? crystal-to-lvds clock generator r evision h istory s heet rev table page description of change date a 1 product discontinuation notice - last time buy expires november 2, 2016. pdn# cq-15-05 11/6/15
corporate headquarters 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 or +408-284-8200 fax: 408-284-2775 www.idt.com technical support email: clocks@idt.com disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or speci cations described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe ci cations and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, wheth- er express or implied, including, but not limited to, the suitability of idt?s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any thi rd parties. idt?s products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reason- ably expected to signi cantly affect the health or safety of users. anyone using an idt product in such a manner does so at th eir own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2015. all rights reserved.

▲Up To Search▲

Price & Availability of 844008AKI-46LF

	To Download 844008AKI-46LF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .